Article ID: 000078290 Content Type: Troubleshooting Last Reviewed: 06/29/2014

Are there any known issues when selecting an Input REFCLK frequency in the Low Latency PHY for a Stratix V GT channel?

Environment

  • Stratix® V GT FPGA
  • Stratix® V FPGAs
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Description

Yes, due to a bug in the Low Latency PHY MegaWizard™, you will be able to select illegal REFCLK frequencies for Stratix® V GT devices. Valid REFCLK frequencies are based on a data rate divider ratio of 16 or 20 and should also take into account the F(max) of the device REFCLK pin.

For example, a 25Gbps data rate would result in either a 781.25MHz or 625MHz REFCLK. As the Fin(max) of the REFCLK pin is 717MHz, the only valid REFCLK frequency would be 625MHz.


This issue will be fixed in a future version of the Quartus® II Software.

Resolution

 

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