Article ID: 000078206 Content Type: Product Information & Documentation Last Reviewed: 12/31/2013

How can we assure that Stratix IV GX/GT and Arria II GX devices meet the PCI Express L0s to L0 transition time limit?

Environment

  • Arria® II GX FPGA
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    PCI Express protocol systems need to support the L0s to L0 state change within 2us for the PCI Express Gen2 and 4us for the PCI Express Gen1. Stratix®  IV GX/GT and Arria®  II GX devices meet this timing if VTX-CM-DC-ACTIVEIDLE-DELTA parameter is less than 25 mV.  If  VTX-CM-DC-ACTIVEIDLE-DELTA parameter is between 25 mV and 60 mV, Altera provides a patch for the Quartus® II software version 9.0 SP2.  Contact Altera My Support to obtain the patch.

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