Article ID: 000078147 Content Type: Error Messages Last Reviewed: 09/11/2012

Warning: PLL |altlvds_tx:altlvds_tx_component |pll have different input signals for input port INCLK



The Quartus® II software may issue this warning when trying to merge PLLs for the ALTLVDS_RX megafunction and the ALTLVDS_TX megafunction with DPA enabled, even though the clock frequencies are the same. This affects Stratix® III and Stratix IV devices.

For example: the PLL post scale divider (k) has a limit range of 1, 2 and 4.  The best VCO frequency for an ALTLVDS megafunction instance without DPA enabled is ~600MHz, however 600MHz cannot be used to generate a 200MHz DPA frequency because 3 is not a valid divider value. 

When using the ALTLVDS megafunction without the external PLL option, you do not have any control over the PLL settings in the Quartus II software.  As a work around, you can use the ALTLVDS megafunction in the external PLL mode.  This allows you control the PLL values and manually assign the PLL clock outputs to the ALTLVDS_RX megafunction and ALTLVDS_TX megafunction instances in your design, thus allowing PLL sharing.

For further information on using ALTLVDS megafunction in external PLL mode refer to the ALTLVDS Megafunction User Guide (PDF).



All postings and use of the content on this site are subject to Terms of Use.