Article ID: 000078140 Content Type: Troubleshooting Last Reviewed: 06/29/2014

Why is the pll_powerdown port of the Stratix V device Transceiver Native PHY IP Core not removed when I enable the “Use external TX PLL” option?

Environment

  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
  • Quartus® II Subscription Edition
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    Description Due to a problem in the Quartus® II software, the pll_powerdown port of the Stratix® V device Transceiver Native PHY IP Core is not removed when the “Use external TX PLL” option is enabled. This pll_powerdown port is not connected to any submodule and you can connect it to '0' in your design.

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