Article ID: 000078113 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why jittery transmitter output is observed in 10G Base R PHY IP for Stratix IV GT?

Environment

  • Stratix® IV GT FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

Below is an transmitter output eye diagram example captured on the 10G Base R PHY IP transmitter output for ACDS 11.0

Figure 1 : Jittery Eye diagram on the transmitter output for 10G Base R PHY IP in ACDS 11.0

The transmitter slew rate was set in-correctly in ACDS 11.0 and above. Figure below show the improved eye diagram after applying the recommanded workaround or software patch. This issue is target be fixed in ACDS 11.1.

Figure 2 : J :Improved eye diagram on the transmitter output for 10G Base R PHY IP in ACDS 11.0

Here are the solutions for ACDS 11.0 and 11.0sp1:

For ACDS 11.0:

Below is the recommanded workaround for ACDS 11.0. Please perform a backup before performing any modification to the Quartus® II library.

  1. Go to Altera® 10G Base R PHY IP root directory:
    • For windows example: C:\altera\11.0\ip\altera\altera_10gbaser_phy\siv
  2. Change the following parameter in siv_10gbaser_pcs_pma_map.v in the PHY IP library folder:
    • For windows example PHY IP library:
        • C:\altera\11.0\ip\altera\altera_10gbaser_phy\siv\siv_10gbaser_pcs_pma_map.v
    • In line 292, change the tx_slew_rate from “low” to “off”
  3. Re-generate the PHY IP megawizard™ and compile the design

For ACDS 11.0SP1:

Please download the appropriate Quartus II software version 11.0SP1 patch 1.07 from the following links:

Quartus II software version 11.0SP1 patch 1.07 for Windows

Quartus II software version 11.0SP1 patch 1.07 for Linux

Quartus II software version 11.0SP1 ReadMe for patch 1.07

Caution:

You must either have previously installed the Quartus II 11.0SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.

After you install the patch or workaround, please regenerate your 10G Base R PHY IP MegaCore® before you compile your design.

Please take note the signal quality shown in figure above may vary due to different transceiver\'s analog setting or PCB design.

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