Article ID: 000078109 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can I read the value of an I/O pin, in core logic, when using the the Bus Hold feature?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, you can read the value of an I/O pin, in core logic, when using the the Bus Hold feature.

You should instantiate the pin as a bi-directional pin.  Using the Bus Hold feature will hold the contents of the output when it is no longer driven (tri-state), you can then read the input side of the bi-directional pin.

Resolution

 

Related Products

This article applies to 37 products

Arria® V GX FPGA
Arria® V GT FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® FPGAs
Arria® II GZ FPGA
Cyclone® II FPGA
Cyclone® V E FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V SE SoC FPGA
HardCopy™ III ASIC Devices
HardCopy™ IV GX ASIC Devices
HardCopy™ IV E ASIC Devices
MAX® II CPLDs
MAX® II Z CPLD
MAX® V CPLDs
Stratix® V GT FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Arria® GX FPGA
Arria® II GX FPGA
Stratix® FPGAs
Stratix® GX FPGA
Stratix® II FPGAs
Stratix® II GX FPGA
Stratix® III FPGAs
Stratix® IV GX FPGA
Cyclone® III FPGAs
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Cyclone® V GX FPGA
Cyclone® V GT FPGA
Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® V GX FPGA