Article ID: 000078019 Content Type: Troubleshooting Last Reviewed: 03/16/2015

Why is a voltage drop observed on an input signal to a Cyclone III or Cyclone IV device during power down?



A voltage drop may be observed on an input signal to a Cyclone® III or Cyclone IV device during power up or power down because the hot socket circuitry will allow currents to flow through the output buffer into ground before VCCINT or VCCIO ramp down completely.

To prevent DC currents to flow from the I/O pins, the VCCINT or VCCIO supplies must be turned off or the VCCIO supply must be powered up to a nominal value and be stable followed by VCCINT or vice versa. Power sequencing may be needed to control power up and power down on these devices for specific system applications.



Turn off the VCCIO supply completely followed by the VCCINT supply or vice versa when powering down the Cyclone III or Cyclone IV FPGA to prevent DC currents flowing from the IO pins.

Related Products

This article applies to 4 products

Cyclone® III FPGAs
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA