Article ID: 000077966 Content Type: Troubleshooting Last Reviewed: 09/21/2012

Ethernet 10G MAC Removal Timing Failure when Compiled without IP License

Environment

  • Stratix® IV FPGAs
  • Quartus® II Subscription Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When users compile Ethernet 10G MAC without its IP license, timing analysis will fail with removal violation. The failing path is driven by "to-clock" of altera_reserved_tck.

    This issue affects Stratix IV devices in ACDS 12.0.

    Resolution

    There is no workaround for this issue.

    This issue is fixed in ACDS 12.1.

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