Article ID: 000077937 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Do Cyclone devices phase-locked loops (PLLs) support the external feedback mode?


  • PLL
    Description No, Cyclone® device PLLs do not have support for the external feedback mode. However, they do support Normal mode, Zero Delay Buffer mode, and No Compensation mode.

    In Normal mode, the PLL feedback path comes from a global clock network that minimizes the clock delay to registers for that specific PLL clock output.

    In Zero Delay Buffer mode, the PLL feedback path is confined to the dedicated PLL external output pin. The clock signal driven off-chip on the PLL_OUT pin is phase aligned with the PLL clock input for a minimized delay between clock input and external clock output. If the PLL is also used to drive the internal clock network, then that clock network also has a corresponding phase shift.

    In No Compensation mode, the PLL feedback path is confined to the PLL loop—it does not come from the global clock network or an external source. There is no clock network compensation, but this mode minimizes jitter on clocks. This mode may lead to positive hold times on I/O element (IOE) registers. You can compensate for this with manual phase shifting.

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    This article applies to 1 products

    Cyclone® FPGAs



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