When using the altlvds megafunction with the external PLL option in Stratix® III, Stratix IV, and Arria® II GX devices, the design examples provided by Altera show the C0, C1, and C2 output counters being used on the PLL. The Quartus® II software automatically rotates the output counters to implement the correct connection scheme. These are the output counters used for the dedicated SERDES:
The C0 (counter 0) output is the parallel clock
The C3 (counter 3) output is the high speed serializer clock
The C5 (counter 5) output should be connected to the enable port
For further information on using the altlvds megafunction with the external PLL option in Stratix III devices, refer to Using altlvds With the External PLL Option in Stratix III FPGAs
For further information on using the altlvds megafunction with the external PLL option in Stratix IV devices, refer to High Speed Differential I/O Interfaces With DPA in Stratix IV Devices (PDF). The procedure shown in this document can also be applied to Arria II GX devices.