Error (11574): ATX PLL node <ATX PLL node name> uses an output frequency of <configured data rate> MHz that exceeds the maximum frequency of 13200.0 MHz in the targeted speed grade <device speed grade> for a Bottom ATX PLL in a transceiver bank

You may encounter the above error if your transceiver channel is configured for a data rate that exceeds 13.2 Gbps in a -1 PMA speed grade Stratix® V device.

This is because the Quartus® II software uses the bottom ATX PLL of a transceiver bank by default. The maximum ATX PLL supported data rate for a bottom ATX PLL is 13.2 Gbps in a -1 PMA speed grade Stratix® V device.

To work around this problem, you can manually place the ATX PLL in the top location of the transceiver bank. The following is an example QSF constraint.

set_location_assignment LCPLL_X0_Y24_N57 -to "llp0:inst|altera_xcvr_low_latency_phy:llp0_inst|sv_xcvr_low_latency_phy_nr:sv_xcvr_low_latency_phy_nr_inst
|sv_xcvr_10g_custom_native:sv_xcvr_10g_custom_native_inst|sv_xcvr_plls:sv_xcvr_native_insts0].
gen_bonded_group_plls.gen_tx_plls.tx_plls|pll[0].pll.atx_pll.tx_pll"

 You can find the top and bottom ATX PLL coordinates from the Quartus® II Chip Planner.

This problem will be fixed in Quartus® II version 15.1 software.