Critical Issue
10GBASE-R PHY v12.0 megafunctions that target Stratix V devices
do not generate rx_use_coreclk
parameters correctly;
the generated HDL file does not pass the rx_use_coreclk
parameter
to the sv_xcvr_10gbaser_nr instance.
Update the generated HDL file to pass the parameter. For a file generated in System Verilog, add the line commented in the example below:
sv_xcvr_10gbaser_nr #(
.num_channels (num_channels ),
.operation_mode (operation_mode ),
.sys_clk_in_mhz (mgmt_clk_in_mhz ),
.ref_clk_freq (ref_clk_freq ),
.rx_use_coreclk (rx_use_coreclk ), //add this line
.pll_type (pll_type ),
.RX_LATADJ (rx_latadj),
.TX_LATADJ (tx_latadj)
)xv_xcvr_10gbaser_nr_inst(