This is an expected behaviour. You will see "Total PLLs" usage is 0 if you only instantiate Intel® Stratix® 10 FPGA E-tile transceiver channels in the design. The Intel® Stratix® 10 FPGA E-tile transceiver channel phase-locked loop (PLL) would not be counted in the total PLLs summary.
For example, if you use Intel® Stratix® 10 device 1ST280EY2F55, and instantiate four E-tile transceiver channels. After compilation, you will still see the “Total PLLs 0/64(0%)” in the flow summary of the compilation report.
All PLLs shown in the compilation report are contributed by the Intel® Stratix® 10 IOPLL and H-tile transceiver PLLs. For Intel® Stratix® 10 device 1ST280EY2F55, the total 64 PLLs consist of 24xIOPLLs, 8xfPLLs of H-tile, 8xATX PLLs of H-tile transceiver, and 24 CDR PLLs of H-tile transceiver. Intel® Stratix® 10 FPGA E-tile transceiver channel PLLs are not counted.