Article ID: 000077221 Content Type: Troubleshooting Last Reviewed: 02/15/2023

Can I enter negative phase shifts in the PLL Intel® FPGA IP?

Environment

    Quartus® II Software
    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II Software v12.0 and earlier, the PLL Intel® FPGA IP does not support negative phase shift entry.

Resolution

To achieve an equivalent phase shift, add one clock cycle (360°) to any required negative phase shift so the result is a positive phase value.

This problem is fixed starting with the Quartus® II Software v12.1 where the PLL Intel FPGA IP supports negative phase shift entry.

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Related Products

This article applies to 4 products

Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Stratix® V E FPGA

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