For cases where your TSE clocks are sourced from internal logic for which a create_clock or create_generated_clock assignment already exists then you are required to modify the TSE sdc file to remove the clock assignments for these clocks.
For Example:
In the case where the TSE input clock "clk" is fed by an internal PLL rather than a top level clock pin then you would receive a warning such as the one below during timing analysis:
Warning: Ignored filter at tse_constraints.sdc(363): clk could not be matched with a port
**Note that the line number may be different depending on the configuration of your TSE core.
The reason for the warning is that the TSE sdc file contains a create_clock assignment for the "clk" input which is no longer required as the "clk" port of the TSE core is now fed from a PLL output which is already constrained.
To avoid the warning simply comment out the create_clock constraint as it is not required.
The solution above applies to any TSE clock which is fed from internal logic rather than a top level pin.
This limitation is scheduled to be resolved in a future release of the Triple Speed Ethernet IP.