Article ID: 000077140 Content Type: Troubleshooting Last Reviewed: 03/04/2014

When using the Stratix V Hard IP for PCI Express, why is the No Command Completed Support (bit 18) of the Slot Capability Register incorrectly set?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Due to a problem in the Stratix® V Hard IP for PCI® Express, this bit is incorrectly set.
Resolution

To work around this problem:

1. Go to:

<your Altera install directory>\<your Quartus® II version>\ip\altera\altera_pcie\altera_pcie_sv_hip_avst\pcie_sv_parameters_common.tcl

2. Replace:

add_parameter          advanced_default_hwtcl_no_command_completed string "true"

with

add_parameter          advanced_default_hwtcl_no_command_completed string "false"

3. Remove:

set_parameter_value no_command_completed_hwtcl "true"

4. Go to:

<your Altera install directory>\<your Quartus® II version>\ip\altera\altera_pcie\altera_pcie_sv_hip_avst\pcie_sv_parameters.tcl

5. Modify the line

if { == 1 } {

set_parameter_value no_command_completed_hwtcl "true"

to:

if { == 1 } {
         set advanced_default_parameter_override  [ get_parameter_value advanced_default_parameter_override ]
                   if { == 0 } {
                      set_parameter_value no_command_completed_hwtcl "true"
                   } else {
                      set_parameter_value no_command_completed_hwtcl  [ get_parameter_value  advanced_default_hwtcl_no_command_completed                          ]
                   }

6. Regenerate the IP core, recompile your design, and simulate.

This problem is scheduled to be fixed in a future version of Quartus® II software.

Related Products

This article applies to 3 products

Stratix® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA

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