Article ID: 000077094 Content Type: Troubleshooting Last Reviewed: 03/07/2023

Line: Invalid data rate! Cell value must be between 0.0 and 1434.0 Skipping!

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see this error when importing an Intel® Quartus® II generated PowerPlay Early Power Estimator (EPE) File into the EPE tool version 13.1 and earlier for a Stratix® V design which contains an ALTLVDS_TX or ALTLVDS_RX mega function that operates at a data rate greater than 1434 Mbps.

 

 

 

Resolution

Intel® Stratix® V devices support data rates up to 1600 Mbps using ALTLVDS, depending upon the speed grade of the device. Refer to the Intel® Stratix® V Device Datasheet (PDF) for detailed specifications.

Related Products

This article applies to 4 products

Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA