Article ID: 000077024 Content Type: Troubleshooting Last Reviewed: 07/01/2020

Why does the Intel® Quartus® synthesis compilation show missing "sdi_cvo_rden" port error when two Clocked Video Output (CVO) II IP core are instantiated in the Intel® Quartus® design ?

Environment

    Intel® Quartus® Prime Pro Edition
    Clocked Video Output II (4K Ready) Intel® FPGA IP
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Critical Issue

Description

Due to the problem in the Intel® Quartus® Prime Pro version 19.2 software and later, the sdi_cvo_rden port is available once "embedded in video" option is checked in Clock Video Output (CVO) II IP core.

The Intel® Quartus® synthesis stage of compilation will  fail with missing "sdi_cvo_rden" port error when two or more CVO II IP are instantiated in the Intel® Quartus® design.

Resolution

No work around to this problem exists.

This problem has been fixed starting in version 20.2 of the Intel® Quartus® Prime Pro software.

Related Products

This article applies to 3 products

Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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