Article ID: 000077020 Content Type: Troubleshooting Last Reviewed: 03/10/2021

Why does the host system receive corrupted data without LCRC error or Completion Time Out error on a PCIe* Gen 3 x16 link that uses the Intel® Stratix® 10 Hard IP for PCI Express* in the Intel® Stratix® 10 L-Tile and H-Tile devices ?

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Stratix® 10 NX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    The Tx FIFO almost full threshold parameter of the Intel® Stratix® 10 Hard IP for PCIe* Gen 3 x16 variant is marginal. You may see corrupted data without LCRC error or Completion Time Out error that does not cause a link recovery to occur.

    Other IP variants like PCIe* Gen 3 x8 and Gen 3 x4 are not affected.

    There is related KDB.

    Why does the system report PCIe* Completion Time out errors on a link that uses the Intel® Stratix® 10 Hard IP for PCI Express in Intel® Stratix® 10 L and H-Tile Devices?

    Resolution

    This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 20.4.

    To resolve this problem, you should regenerate the Intel® Stratix® 10 Hard IP for PCIe* Gen 3 x16 variant and recompile the design with the Intel® Quartus® Prime Pro Edition software version 20.4 or later version to incorporate the fix.

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