Article ID: 000080771 Content Type: Troubleshooting Last Reviewed: 10/07/2020

Why does the system report PCIe* Completion Time out errors on a link that uses the Intel® Stratix® 10 Hard IP for PCI Express in Intel® Stratix® 10 L and H-Tile Devices?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro edition software version 20.2, you may see Completion Time out errors on a PCIe link that uses the Intel® Stratix® 10 Hard IP for PCI Express in the Intel® Stratix® 10 L and H-Tile devices.

    Resolution

    No workaround for this problem exists in version 20.2 of the Intel® Quartus® Prime Pro edition software.

    This problem has been fixed in the Intel® Quartus® Prime Pro edition software version 20.3 or later.

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