Article ID: 000076997 Content Type: Troubleshooting Last Reviewed: 06/22/2017

Why does the mem_reset_n signal toggle multiple times at the first assertion in the Skip Calibration simulation mode?

Environment

  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This observation is expected and does not cause any malfunction of the PHY operation during simulation. In Full Calibration simulation mode, the EMIF IP performs a full reset initialization sequence, and consequently, those glitches don't occur.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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