Article ID: 000076910 Content Type: Troubleshooting Last Reviewed: 01/25/2022

Why does the High Bandwidth Memory (HBM2) Interface IP example design in the Intel® Stratix® 10 MX FPGA show min pulse width violation?

Environment

  • Intel® Quartus® Prime Pro Edition
  • High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1 and earlier, you may see the min pulse width violation if you create an example design for the High Bandwidth Memory (HBM2) Interface IP targeting the Intel® Stratix® 10 MX FPGA. 

    Resolution

    To work around this problem, download and install the Intel® Quartus® Prime Pro Edition Software version 19.1 patch 0.04 from the appropriate link below. After installing the patch, follow the steps shown in the Readme file.

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.2.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 MX FPGA