Article ID: 000076833 Content Type: Troubleshooting Last Reviewed: 07/21/2020

Why does my Intel® P-Tile Avalon®-ST for PCI Express* IP RX interface behave differently depending on the reset condition?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 DX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Intel® P-Tile Avalon®-ST for PCI Express* IP implements a deskew module in the FPGA fabric to realign receive side packets coming from Embedded Multi-die Interconnect Bridge (EMIB) interface. The deskew module has a reset problem that could cause misalignment on the Avalon-ST RX interface.

    Resolution

    This problem is fixed in the Intel® Quartus® Prime Pro Edition software version 20.1. 

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