Article ID: 000076798 Content Type: Troubleshooting Last Reviewed: 03/16/2018

Is there a known issue with Intel® Stratix® 10 3V IOs in user mode?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, due to a known problem in Intel® Quartus® Prime Pro software version 17.1 update 2 or earlier, when 3V IOs in Intel Stratix® 10 FPGAs are assigned to a static GND in the design, you may see an inversion at the output pin. 

    3V IOs are located in IO banks 6A,6B,6C,7A,7B,7C and are available in different density and package variants of Intel Stratix 10 devices.

    Resolution

    To work around this, use an input to drive the 3V IO or place the signal assignment in a clocked process. 

    This is scheduled to be fixed in a future release of the Intel Quartus Prime Pro software. 

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.