Yes. There are two issues that affect ALTMEMPHY-based DDR2 and DDR3 SDRAM memory interface designs. These issues affect the Stratix® III, Stratix IV, HardCopy® III, and HardCopy IV devices. All ALTMEMPHY-based memory interface designs generated using Quartus® II software versions 9.1 SP1 and earlier are affected.
1. OCT Timing: The OCT timing issue affects all DDR2 SDRAM interface designs and discrete DDR3 SDRAM interface designs (without read/write leveling) that use the dynamic OCT feature. All high-performance controller I and II (HPC I & HPC II) designs are affected with the exception of HPC I half-rate DDR2 designs.
In affected designs, the dynamic OCT signal timing is incorrect for read-to-write bus turnarounds. This can lead to the corruption of data written to the memory. These designs must implement the fix provided in the Quartus II software patch to ensure productionworthiness.
2. IO Clocking Topology: In designs implementing DDR3 interfaces with read/write leveling, the I/O clocking topology used to transfer data between resynchronization registers within the IO element is not optimal. However, no hardware failures have been observed or reported. The Quartus II software patch optimizes the I/O clocking topology and improves timing margins. The software fix is recommended as a precaution for leveled DDR3 designs.
This issue has been fixed in Quartus® II software version 9.1 SP2. Patches 0.74 and 1.09 are available to fix these problems in Quartus II software versions 9.1 and 9.1 SP1, respectively.
The ALTMEMPHY sequencer RTL has been updated to address these issues. To fix the problem, download and install the Quartus II software service pack or patch, regenerate all affected ALTMEMPHY-based memory interface instances, and recompile your design.