When using the ALTLVDS Megafunction in “External PLL” mode you may get the following warning:
Warning: The DPA clock of SERDES receiver atom "rx" is driven by PLL "xxxxxxx" with unspecified dpa_multiply_by and dpa_divide_by parameters
When using the ALTLVDS Megafunction in “External PLL” mode, the ALTPLL megafunction must have a method to specify the dpa_multiply_by and dpa_divide_by parameters, which are necessary in DPA applications. These parameters must be set the same as the corresponding clk_multiply_by/divide_by parameters for the clock that feeds the ALTLVDS clock port (i.e. high-speed clock with frequency equal to the datarate). If the ALTPLL megafunction does not have a check box option on the Output Clocks settings page that says "Use these clock settings for the DPA clock", then you will have to manually edit the generated ALTPLL instance and set the dpa_multiply_by/dpa_divide_by parameters.
The following examples assumes that your multiply and divide settings are 10 and 1 respectively.
--Example Manual Edit to the ALTPLL Component Declaration Generic Map (VHDL)
dpa_multiply_by : integer;
dpa_divide_by : integer;
--Example Manual Edit to the ALTPLL Generic (VHDL)
dpa_multiply_by => 10, -- Set these according to your PLL settings
dpa_divide_by => 1, -- Set these according to your PLL settings
-- Example Manual Edit to the ALTPLL defparam (Verilog)
altpll_component.dpa_multiply_by = 10,
altpll_component.dpa_divide_by = 1,