Article ID: 000076653 Content Type: Troubleshooting Last Reviewed: 12/19/2014

DDR3 VHDL Simulation in Max 10 Fails with Aldec Riviera-PRO

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

This problem affects DDR3 interfaces on MAX 10 devices.

For DDR3 interfaces on MAX 10 devices, VHDL simulation with the Aldec Riviera-PRO simulator may fail.

Resolution

The workaround for this issue is to use a simulator other than Aldec Riviera-PRO, for simulation of DDR3 interfaces on MAX 10 devices.

This issue will be fixed in a future version.

Related Products

This article applies to 1 products

Intel® MAX® 10 FPGAs

1