Article ID: 000076626 Content Type: Troubleshooting Last Reviewed: 09/09/2020

Why does the CDR fail to lock in 25G mode when using the E-Tile Hard IP for Ethernet when the PHY reference frequency is set to 312.5MHz on the Intel® Stratix® 10 and the Intel® Agilex™ E-tile FPGAs?

Environment

  • Intel® Agilex™ FPGAs and SoC FPGAs
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, the CDR can't lock in 25G mode when using the E-Tile Hard IP for Ethernet when the PHY reference frequency is set to 312.5MHz.

    Resolution

    There is no workaround for this problem as the 312.5MHz is not in the supported range for the E-Tile PHY IP. Use a reference clock frequency of 156.25MHz or 322.265625MHz.

     

    This 312.5MHz reference clock frequency option is scheduled fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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