Article ID: 000076626 Content Type: Troubleshooting Last Reviewed: 03/10/2023

Why does the CDR fail to lock in 25G mode when using the E-Tile Hard IP for Ethernet when the PHY reference frequency is set to 312.5MHz on the Intel® Stratix® 10 and the Intel Agilex® 7 devices?

Environment

    Intel® Quartus® Prime Pro Edition
    Ethernet
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Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier, the CDR can't lock in 25G mode when using the E-Tile Hard IP for Ethernet when the PHY reference frequency is set to 312.5MHz.

 

 

 

 

Resolution

This problem has no workaround, as the 312.5MHz is not in the supported range for the E-Tile PHY IP. So instead, use a reference clock frequency of 156.25MHz or 322.265625MHz.

 

This 312.5MHz reference clock frequency option is fixed in Intel® Quartus® Prime Pro Edition Software version 21.1.

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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