Critical Issue
Due to a problem with the Cyclone® 10 DDR3 IP, the generated example design simulates the emif_usr_clk frequency inaccurately.
For instance, if the example design is set with a memory clock frequency = 533.33MHz, clock rate of user logic = Quarter, and the PLL_refclk = 133.33MHz, then the expected emif_usr_clk should simulate at 133.33MHz.
However, you may observe the emif_usr_clk at 7.52ns = 133MHz in the simulation waveform viewer.
The workaround is to manually edit the simulation design file (for example, the directory path may look like the following: /emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_c10_180/sim/ed_sim_emif_c10_0_altera_emif_c10_*_*.v).
For the example below, search for the parameters and edit them to the correct period value to match the desired frequency.
1445: .PLL_VCO_FREQ_MHZ_INT (533),
1446: .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (1),
1447: .PLL_PHY_CLK_VCO_PHASE (2),
1448: .PLL_VCO_FREQ_PS_STR ("1876 ps"),
1449: .PLL_REF_CLK_FREQ_PS_STR ("7504 ps"),
1450: .PLL_REF_CLK_FREQ_PS (7504),
1451: .PLL_SIM_VCO_FREQ_PS (1880),
1452: .PLL_SIM_PHYCLK_0_FREQ_PS (3760),
1453: .PLL_SIM_PHYCLK_1_FREQ_PS (7520), // example : change this value from 7520 to 7500
1454: .PLL_SIM_PHYCLK_FB_FREQ_PS (7520), // example : change this value from 7520 to 7500
1455: .PLL_SIM_PHY_CLK_VCO_PHASE_PS (470),
1456: .PLL_SIM_CAL_SLAVE_CLK_FREQ_PS (7520), // example : change this value from 7520 to 7500
1457: .PLL_SIM_CAL_MASTER_CLK_FREQ_PS (7520), // example : change this value from 7520 to 7500
After saving the edited parameters, then re-run the simulation to reflect the correct frequency.