Article ID: 000076604 Content Type: Troubleshooting Last Reviewed: 11/18/2011

VHDL-Generated Fileset Can Encounter Synthesis Problems for UniPHY External Memory Interfaces

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

An error in the VHDL-generated wrapper for the synthesis fileset can result in a variety of synthesis problems.

Resolution

The workaround for this issue is to open the generated wrapper file in a text editor, and replace all ports of the form std_logic_vector(0 downto 0) with std_logic .

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.