Article ID: 000076597 Content Type: Troubleshooting Last Reviewed: 10/29/2015

** Warning nofile(37) in protected region.

Environment

    Simulation
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description You may experience the above warning while simulating a VHDL-based DDR3 UniPHY memory controller with ModelSim. When the DDR3 memory controller is generated in VHDL, all Verilog and SystemVerilog submodules are encrypted to allow simulation with a single-language simulator. If a warning occurs in the encrypted fileset, a cryptic message like the one above will be generated.
Resolution

Make sure the DDR3 files are being compiled in the order specified in the msim_setup.tcl file in the <variation_name>_sim directory. Any files compiled out-of-order may result in the above warning.

If you still see the above warning after compiling the files in the correct order, you will need to create a Verilog-based DDR3 UniPHY memory controller and use the unencrypted Verilog and SystemVerilog files in place of the encrypted fileset to isolate the source of the warning. This requires a dual-language simulator like ModelSim SE.

Related Products

This article applies to 19 products

Cyclone® V GT FPGA
Cyclone® V SX SoC FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs
Stratix® IV GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA
Stratix® IV E FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.