Article ID: 000076578 Content Type: Troubleshooting Last Reviewed: 07/06/2020

When using the Intel® FPGA P-Tile Avalon® memory-mapped IP for PCI* Express, why is the "PCIe0 Link" tab in GUI missing?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 DX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    In v20.1 of the Intel® Quartus® Prime Pro Edition software, the Intel® FPGA P-Tile Avalon® memory-mapped IP for PCI* Express "PCIe0 Link" tab is missing from the IP GUI.

    This problem prevents the user from enabling or disabling the "Slot Clock" reference clock from the connector.

    Resolution

    This problem has been fixed starting in v20.2 of the Intel® Quartus® Prime Pro Edition software.

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