Article ID: 000076537 Content Type: Troubleshooting Last Reviewed: 06/23/2017

Why is tx_transfer_status asserted after the Low Latency Ethernet 10G MAC IP core is configured to the 1Gbps data rate?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Triple-Speed Ethernet Intel® FPGA IP
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
  • 1G 2.5G 5G 10G Multi-rate Ethernet PHY Intel® FPGA IP
  • Ethernet 10G MAC Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This problem can be observed if the TSE MegaCore 1G PHY is connected with the Low Latency Ethernet 10G MAC Megacore.

    The Low Latency Ethernet 10G MAC Megacore does not support TSE 1G PHY connections. This information is available in Low Latency Ethernet 10G MAC User Guide

     

    Resolution

    The following configurations are supported:

    Use the Multi-Rate Ethernet PHY IP Megacore with Low Latency Ethernet 10G MAC IP core.

    or

    Use the TSE 1G PHY Megacore with the legacy 10GbE MAC IP core.

    Related Products

    This article applies to 4 products

    Stratix® V FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.