Article ID: 000076533 Content Type: Product Information & Documentation Last Reviewed: 09/23/2020

How do I use the channel_reset port in the 25G Ethernet Intel® Stratix® 10 FPGA IP?

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Stratix® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
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    Description

    Due to a mistake in the UG-20109 | 2020.04.13, there is no description of channel_reset port for 25G Ethernet Intel® Stratix® 10 FPGA IP. The channel_reset port is a reset input that is only present if the Enable 10G/25G Dynamic Rate Switching option is checked. Before initiating reconfiguration between speeds, assert this signal to hold the TX/RX data paths in reset. 

    Resolution

    This missing information has been added in UG-20109 | 2020.07.29.

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