Article ID: 000076493 Content Type: Troubleshooting Last Reviewed: 01/17/2023

When using the Low Latency 10G MAC IP core in Intel® Arria® 10 devices, how should the transceiver PLLs be placed to reduce jitter?


  • Quartus® II Subscription Edition
  • 1G 2.5G 5G 10G Multi-rate Ethernet PHY Intel® FPGA IP
  • Ethernet
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
  • 1G 10GbE and 10GBASE-KR PHY Intel® Arria® 10 FPGA IP

    To minimize jitter when using the Low Latency 10G MAC IP core on Intel® Arria® 10 devices, it is important to ensure that the advanced transmit (ATX) phase-locked loop (PLL) and the fractional PLL (fPLL) be placed so that they can source the input reference clock directly from the reference clock buffer without passing through the reference clock network.


    For best jitter performance, Intel recommends placing the reference clock as close as possible to the transmit PLL.

    Use a dedicated reference clock pin in the same transceiver bank.

    There are two dedicated reference clock (refclk) pins available in each transceiver bank. The bottom refclk pin directly feeds the bottom ATX PLL, fPLL, and CMU PLL. The top refclk pin directly feeds the top ATX PLL, fPLL, and CMU PLL.

    Use a location constraint to ensure that the ATX PLL and fPLLs are located in the optimal top or bottom location, aligned with your chosen dedicated refclk pin location.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs