Article ID: 000076484 Content Type: Troubleshooting Last Reviewed: 02/09/2023

Why is there port width mismatch when I try to connect the encoder output directly to the decoder input of the LDPC Intel® FPGA IP core?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® FPGA IP Low-Density Parity-Check (LDPC) IP-LDPC
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The output of the LDPC Intel® FPGA IP core encoder cannot be connected directly to the input of the LPDC Intel FPGA IP core decoder. The output data of encoder will need to undergo log-likelihood ratio (LLR) and soft bits conversion prior to feeding into input of the decoder. You will need to create the conversion logic using the soft logic.

Resolution

There is no workaround required.

Related Products

This article applies to 10 products

Cyclone® IV FPGAs
Cyclone® V FPGAs and SoC FPGAs
Intel® MAX® 10 FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Stratix® V FPGAs
Stratix® IV FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 FPGAs
Arria® V FPGAs and SoC FPGAs
Arria® II FPGAs

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