Article ID: 000076481 Content Type: Troubleshooting Last Reviewed: 04/19/2017

RapidIO MegaCore Function User Guide Has Incorrect Information About the Port 0 Error and Status CSR

Environment

    Intel® Quartus® Prime Pro Edition
    RapidIO (IDLE1 up to 5.0 Gbaud) Intel® FPGA IP
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Description

According to the RapidIO MegaCore Function User Guide, any of the following three link protocol violations causes the RapidIO IP core input port to transition to the Input Error Stopped state, setting the IN_ERR_STOP bit of the Port 0 Error and Status CSR (offset 0x158):

Unexpected packet-accepted control symbol

Unexpected packet-retry control symbol

Unexpected packet-not-accepted control symbol

However, these conditions do not affect the input port. Instead, they cause the RapidIO output port to transition to the Output Error Stopped state, and set the OUT_ERR_STOP of the Port 0 Error and Status CSR.

Resolution

This issue has no workaround. Ensure you use the explanation in this erratum to interpret the values in the Port 0 Error and Status CSR.

This issue is fixed in version 17.0 of the RapidIO IP Core User Guide.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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