In Stratix® III and Cyclone® III devices, designs using the Dynamic Phase Stepping feature may see situations where the wrong output clock is phase adjusted if the phasecounterselect port is fed by a constant. This affects Quartus® II design software version 7.2 SP3 and prior.
If this situation occurs, insert extra logic in front of the altpll phasecounterselect port or register the constant that feeds this port. In the latter case, you may need to use the preserve attribute to prevent the registers being synthesized away.
This is resolved in the Quartus II software version 13.0.