Critical Issue
Description
The testbench for a RapidIO MegaCore function x1 5.00 Gbaud variation that targets an Arria V device might fail simulation because of a reference clock frequency that causes byte ordering mismatches from the RX transceiver.
Resolution
To avoid this issue, set the reference clock frequency to 200 MHz or 500 MHz in the RapidIO parameter editor before generating your RapidIO MegaCore function.
This issue is fixed in version 11.1 SP2 of the RapidIO MegaCore function.