Article ID: 000076426 Content Type: Troubleshooting Last Reviewed: 03/16/2020

Why does the E-tile Hard IP Intel® Stratix® 10 25G Ethernet to CPRI Dynamic Reconfiguration Design Example Modelsim simulation run never end ?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • Intel® CPRI
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition version 19.3 Software, the design example Modelsim simulation run will get stuck at the last stage of dynamic reconfiguration operation and not complete the simulation.

    • # INFO: Starting dynamic reconfiguration: 2.4G CPRI --> 25G PTP RSFEC 
    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition version 19.4 software 

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.