Article ID: 000076420 Content Type: Troubleshooting Last Reviewed: 06/22/2020

When using the Intel® FPGA P-Tile Avalon® streaming IP for PCI* Express, why is an error seen when "Enable Completion Timeout Interface" is selected?

Environment

  • Intel® Stratix® 10 DX FPGA
  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    Due to a problem with the Intel® FPGA P-Tile Avalon® streaming IP for PCI* Express, and error of the form shown below will be seen if the option "Enable Completion Timeout Interface" is selected in the IP GUI.

    Error: intel_pcie_ptile_ast_0.dummy_user_avmm_rst has an associatedClock of "p0_hip_reconfig_clk" which could not be found

    This is due to the completion timeout interface being incorrectly associated with the hip_reconfig_clk. This error prevents the IP from being generated.

    Resolution

    In v20.1 of the Intel® Quartus® Prime Pro Edition of software, no workaround to this problem exists, generate the IP with the option "Enable Completion Timeout Interface" disabled.

    This problem has been fixed starting in v20.2 of the Intel® Quartus® Prime Pro Edition of software.

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