Article ID: 000076401 Content Type: Product Information & Documentation Last Reviewed: 09/17/2014

How do I calculate the value of the static timing adjustment registers of the Low Latency Ethernet 10G MAC MegaCore?

Environment

    Ethernet
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Description

To calculate the value of the static timing adjustment registers it is necessary to convert the TX/RX PMA delay to hexadecimal and set it to associated static timing adjustment register such as tx_ns_adjustment_10G of the Low Latency Ethernet 10G MAC MegaCore®.

Example for Arria V GZ 40-bits PMA mode:

  1. Find the PMA delay in the Low Latency Ethernet 10G MAC MegaCore user guide
    • 10G hardware digital Tx delay = 123 UI x 0.097 ns = 11.931 ns
    • 10G hardware analog Tx delay = -1.1 ns
  2. Calculate the total delay
    • 11.931 ns - 1.1 ns = 10.831 ns
  3. Convert the nanoseconds to hexadecimal
    • 10 ns = 0x000A
  4. Multiply the fractional nanoseconds by 65,536 (0x10000)
    • 0.831 ns x 65,536 = 54,460.416
  5. Round the multiplied fractional nanoseconds to unit
    • 54,460.416 => 54,460
  6. Convert the rounded fractional nanoseconds to hexadecimal
    • 54,460 = 0xD4BC
  7. Set the converted delay value to associated register
    • tx_ns_adjustment_10G = 0x000A
    • tx_fns_adjustment_10G = 0xD4BC

 

Related Products

This article applies to 8 products

Stratix® V GX FPGA
Stratix® V E FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA

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