Why is the read data value incorrect for the DQS input delay when using the Dynamic Reconfiguration mode in the Intel® Arria® 10 PHYLite IP?

When using the Dynamic Reconfiguration mode in the Intel® Arria® 10 PHYLite IP, you may write a value for the DQS input delay to a specific address location.

However, you may see a different data value for the DQS input delay when reading back from that specific location because the legal range of the DQS input delay isn’t fixed and is dependent on the VCO frequency.

A typical calibration methodology is to sweep the DQS input delay for pass/fail results. An expected calibration is to increment the DQS Input delay through a valid range and capture the largest value before it passes. Then continue to increment the DQS input delay and capture the smallest value before it fails. The DQS input delay is then set to the mid-point of the above two values.

However, the entire 10-bit range value for the DQS input delay (i.e. 0X3FF) won’t be available for slower interface frequencies because there exists only a limited number of delay cells where each cell has a Process, Voltage, and Temperature (PVT) dependent fixed delay value. The Intel® Arria® 10 PHYLite circuit caps the DQS Input delay to a legal maximum value.

Therefore, if you write a value for the DQS input delay greater than the maximum DQS input delay, then you will actually write a value equal to the maximum DQS input delay and you will read back a value equal to the maximum DQS input delay.

Below is a table showing some select Intel® Arria® 10 PHYLite clock frequencies and the maximum DQS input delay.

Note: The maximum DQS input delays differ as they depend on the device Process, Voltage, and Temperature (PVT).

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.