Article ID: 000076373 Content Type: Error Messages Last Reviewed: 09/11/2012

Error "GXB REFCLK divider could not be added after signal "rx_cruclk[0]" because it feeds cruclk port of GXB Receiver channel “alt2gxb:alt2gxb_component| channel_rec[0].receive" that uses channel interface or channel internals reconfiguration"

Environment

  • Stratix® II GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The below fitter error occurs if the ALT2GXB Megawizard® Plug-in Manager instantiation in the compiled design has  the  following configuration. The channel is a full duplex or receive only, channel internals or channel interface is enabled, and the input clock frequency, specified in the ALT2GXB Megawizard is greater than 325 MHz. This error does not occur for a TX only configuration.

 

Quartus® II software fitter error: "GXB REFCLK divider could not be added after signal "rx_cruclk[0]" because it feeds cruclk port of GXB Receiver channel  alt2gxb:alt2gxb_component| channel_rec[0].receive" that uses channel interface or channel internals reconfiguration"

 

To workaround this error, use the following procedure.

1. Change the input clock frequency(>325 MHz) in the ALT2GXB Megawizard to half the value.

2. Instantiate the REFCLK divider code (shown below) in your design and connect the REFCLK divider output to the ALT2GXB clock input ports.

For the duplex configuration, connect the  REFCLK divider output to the ALT2GXB clock input ports.  If the specified input clock frequency in the 'General' screen of the ALT2GXB Megawizard is greater than 325MHz then connect the REFCLK divider output to the 'pll_inclk' and 'rx_cruclk' ports of the ALT2GXB instantiation. If the above frequency is specified in the 'RECONFIG' screen, connect the REFCLK divider output to the 'pll_inclk_alt' and 'rx_cruclk_alt' ports.

For example, if you have a full-duplex configuration and if you have specified 390.625 MHz in the 'General' screen of the ALT2GXB Megawizard, change the frequency to 195.3125 MHz and connect the REFCLK divider output to the pll_inclk and rx_cruclk ports of the ALT2GXB.

For a receive-only ALT2GXB instantiation, change the input frequency (>325 MHz) in the Megawizard to half the value and connect the REFCLK divider output to the rx_cruclk or rx_cruclk_alt ports based on the input reference clock frequency settings in the 'General' or 'Reconfig' screen in the Megawizard.

//The following is an example REFCLK divider code in Verilog and VHDL.

//------ Verilog Code for Clock Division---------
module my_refclk_div(in, out);
input in;
output out;
stratixiigx_hssi_refclk_divider my_refclk_divider (
 .inclk(in),
 .clkout(out));
defparam my_refclk_divider.enable_divider = "true";
defparam my_refclk_divider.divider_number = 0;
defparam my_refclk_divider.refclk_coupling_termination = "normal_100_ohm_termination";
endmodule

//-----End

--VHDL Code for Clock Division----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY my_refclk_divider IS
PORT
(
 inclk:   in std_logic;
 outclk: out std_logic

);
end my_refclk_divider;

architecture clock_div of my_refclk_divider is
component stratixiigx_hssi_refclk_divider IS
    GENERIC (
        enable_divider : STRING := "true";
        divider_number : INTEGER := 0;  -- 0 or 1 for logical numbering
        refclk_coupling_termination : STRING := "normal_100_ohm_termination"     
                      );

    PORT (
        inclk                   : IN STD_LOGIC;  
        clkout                 : OUT STD_LOGIC);  
 
END component stratixiigx_hssi_refclk_divider;

begin
clk_divider: stratixiigx_hssi_refclk_divider
port map
(
inclk => inclk,
clkout => outclk
);

end architecture;

 

 

 

 

 

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