When the HPS preloader is compiled from handoff files generated by the Quartus® II software versions 13.1.1 and 13.1.2, SDRAM calibration will fail immediately in Stage 1, Sub-Stage 1. An error message similar to the message shown below will be output to the console:
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U-Boot SPL 2012.10
SDRAM : Initializing MMR registers
SDRAM : Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION FAILED
### ERROR ### Please RESET the board ###
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When calibration debug report for SoC devices is enabled, an error message similar to the message shown below will be output on the console:
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U-Boot SPL 2013.01.01 BOARD : Altera SOCFPGA Cyclone V Board
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION FAILED
SEQ.C: Calibration Summary
SEQ.C: Calibration Failed
SEQ.C: Error Stage : 1
SEQ.C: Error Substage: 1
SEQ.C: Error Group : 0
### ERROR ### Please RESET the board ###
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This error occurs when the preloader handoff files are generated by the Quartus II software versions 13.1.1 and 13.1.2, regardless of the version of SoC EDS used to compile the preloader.
This error is fixed in the Quartus II software version 13.1.3. To resolve this error, regenerate your SoC system in QSys version 13.1.3, recompile your design in version 13.1.3 of the Quartus II software, and regenerate the SoC preloader.