Article ID: 000076360 Content Type: Troubleshooting Last Reviewed: 09/14/2017

What is the maximum payload size I can issue the PCI Express Hard IP on the Avalon-ST TX interface?

Environment

    Quartus® II Subscription Edition
    Cyclone® V Hard IP for PCI Express Intel® FPGA IP
    IP_Compiler for PCI Express
    Stratix® V Hard IP for PCI Express Intel® FPGA IP
    Stratix® V Hard IP for PCI Express with SR-IOV Intel® FPGA IP
    PCI Express
    Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
    Arria® V GZ Hard IP for PCI Express Intel® FPGA IP
    Arria® V Hard IP for PCI Express Intel® FPGA IP
    Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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Description

In Avalon-ST mode, the user logic is required to ensure that the TX TLP presented to the PCI* Express IP core is no larger than the negotiated Max Payload size.

Related Products

This article applies to 17 products

Stratix® IV GX FPGA
Intel® Stratix® 10 FPGAs and SoC FPGAs
Stratix® V GS FPGA
Stratix® V GT FPGA
Arria® GX FPGA
Arria® II FPGAs
Arria® V FPGAs and SoC FPGAs
Intel® Cyclone® 10 GX FPGA
Cyclone® IV GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Stratix® II GX FPGA
Stratix® IV GT FPGA
Stratix® V GX FPGA

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