Description
Due to a problem with the Serial Lite III Streaming Intel® FPGA IP core, you may observe the above error during compilation with the Intel® Quartus® Prime Pro Edition version 19.4 if you are trying to merge two simplex instances into the same Intel® Stratix® 10 H-Tile transceiver channel. This is because the background calibration is enabled by default for all data rate.
Resolution
There is no workaround for this problem. This problem is fixed in the Intel® Quartus® Prime Pro Edition software version 20.2.