Critical Issue
Description
This problem affects LPDDR2 products.
LPDDR2 designs targeting Cyclone V devices at 300 MHz or 333 MHz will fail in hardware due to a hard memory controller bit setting mismatch in the SRAM Object File (.sof).
Resolution
The workaround for this issue is to run LPDDR2 designs with hard memory controller on Cyclone V devices at 200 MHz or 267 MHz rather than at 300 MHz or 333 MHz. If you are using an LPDDR2-S4 memory device, change the tCCD value from 1 to 2.
This issue is fixed in release 12.1 SP1 DP1.