Article ID: 000076289 Content Type: Troubleshooting Last Reviewed: 07/09/2019

Why does the Intel® Stratix® 10 HBM2 IP calibration success signal stay low at Tj less than 0°C ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The minimum operating temperature for HBM2 DRAM is 0°C. When the Intel® Stratix® 10 MX FPGAs must be configured at less than 0°C, the HBM2 controller will read the junction temperature (Tj) using the TSD (temperature sense diode) and will hold the controller in reset.  The local_cal_success signal and AXI_*_ready signals won't be asserted until Tj reaches 0°C or greater.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA

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