Article ID: 000076276 Content Type: Troubleshooting Last Reviewed: 02/21/2019

Why does my Intel® Stratix® 10 device fail to configure if there is a delay between power up and configuration?


  • Intel® Quartus® Prime Pro Edition

    Critical Issue


    Due to a problem in the Intel® Stratix® 10 devices listed below, if it takes longer than 18 seconds from the completion of power up to the configuration of the first 256 Kb of configuration bitstream your Stratix® 10 device may fail to configure. 

    The root cause lies in the Boot ROM, which causes a watchdog timer to overflow and causes the device to hang.  This issue applies to all configuration schemes. Configuration via Protocol (CvP) is not impacted if the programming of the periphery meets the 18 seconds requirement as described in the workaround. This issue does not apply to reconfiguration.

    If you are using the Intel FPGA Download Cable II and you encounter this issue, you will see the following error message: Error (20068): Configuration error, you must power-cycle the device to recover from this condition. To avoid this error, you must ensure that the device is configured within 18 seconds after completion of the power-on sequence.

    This issue affects the following Intel Stratix 10 devices:

    Impacted Stratix 10 GX variants

    • Intel Stratix 10 GX 1100 H-Tile ES1
    • Intel Stratix 10 GX 2800 H-Tile ES2
    • Intel Stratix 10 GX 2800 H-Tile ES3
    • Intel Stratix 10 GX 2800 L-Tile ES3
    • Intel Stratix 10 GX 2500 L-Tile Production
    • Intel Stratix 10 GX 2800 L-Tile Production


    Impacted Stratix 10 SX variants

    • Intel Stratix 10 SX 1100 H-Tile ES1
    • Intel Stratix 10 SX 2800 L-Tile ES1
    • Intel Stratix 10 SX 2800 L-Tile ES2
    • Intel Stratix 10 SX 2800 L-Tile ES3
    • Intel Stratix 10 SX 2800 H-Tile ES3


    Impacted Stratix 10 MX variants

    • Intel Stratix 10 MX 2100 H-Tile ES1


    Impacted Stratix 10 TX variants

    • Intel Stratix 10 TX 2800 ES1
    • Intel Stratix 10 TX 2100 ES1

    The recommended conditions for configuration are shown in Figure 4 of the Intel Stratix 10 Configuration User Guide. After successful configuration the nSTATUS pin is driven high within 110 ms of nCONFIG pin transitioning to high. The observed behavior with impacted devices shows that the nSTATUS pin remains low until the device is power cycled.


    There are both hardware and software workarounds possible for this issue, which are described in the errata document. The hardware and software workarounds are common to all impacted Intel® Stratix® 10 device variants. To implement the software workaround, you are required to download and install patch 0.13 along with Intel® Quartus® Prime Pro Edition version 18.0 from the below links. 

    Patch 0.13 Link (Microsoft Windows 10) : Download 

    Patch 0.13 Link (Linux) : Download


    This problem is due to be fixed in the production version of the Intel Stratix 10 SX 2800/2500 L-Tile device.  If you are using an Intel Stratix 10 GX 2800/2500 L-Tile device and a fix is required, move to the Intel Stratix 10 SX 2800/2500 L-Tile device, which is drop-in compatible.

    Related Products

    This article applies to 2 products

    Intel® FPGA Configuration Devices
    Intel® Stratix® 10 FPGAs and SoC FPGAs